1. Field of the Invention
The present invention relates in general to integrated circuit testers and in particular to a tester that uses a disk drive as a source of data during a test.
2. Description of Related Art
A typical integrated circuit (IC) tester includes a separate channel for each terminal of an IC to be tested. Each channel includes a pin electronics circuit capable of either supplying a test signal to the IC terminal or sampling the state of an IC output appearing at the terminal to determine its state. A typical IC tester organizes a test into a succession of test cycles, and prior to each test cycle the pin electronics circuit of each channel receives an input "vector" (instruction) referencing the test activity that the pin electronics circuit is to carry out during the test cycle. Each tester channel also includes a vector memory for storing the sequence of vectors to be supplied to the local pin electronics circuit during the test. The tester is programmed by loading an appropriate vector sequence into the vector memory of each channel. During the test, a sequencer sequentially addresses the vector memory in each channel so that it reads out a vector for each test cycle and delivers it to the pin electronics circuit.
In addition to normal input and output terminals, some ICs also include "scan" terminals which enable a tester to ascertained states of internal IC nodes at some point during a test. When the tester supplies an appropriate serial data sequence to one of the ICs scan terminals, the IC produces an output data sequence at another of the IC's scan terminals indicating the states of various internal IC nodes. When an IC test reaches the point at which the states of various internal nodes are to be ascertain, the tester channels that drive normal IC input terminals hold their output test signals to particular states while the channels accessing the scan terminals supply input scan data to the IC and acquire the resulting IC output scan data.
During normal test cycles, the tester channels that access scan terminals are "idle" because they don't send input scan data to or acquire output scan data from the IC. But each channel accessing a scan terminal still requires an input vector during each normal test cycle to hold it to a proper state during the test cycle. Thus the vector memory for a channel accessing a scan terminal must not only provide a vector to tell the channel what to do during each scan test cycle, it must also provide a vector for every normal test cycle as well. During scan test cycles the tester channels accessing normal IC input and output are "idle" in that they simply hold IC input signal to fixed states and cease sampling IC output signals. Nonetheless each such tester channel accessing an IC input or output terminal still requires an input vector to tell it what to do during each scan test cycle. Thus regardless of whether a tester channel accesses a normal IC input/output terminal or a scan terminal, its vector memory must store and provide a vector for every normal test cycle and for every scan test cycle. When a test involves large numbers of both normal and scan test cycles, vector memories have to be big.
Programmable logic devices (PLD's) such as field programmable gate arrays are programmed to carry out various logic operations by programming data sequences applied to special programming input terminals. When an IC tester tests a PLD it uses one tester channel to supply a sequence of programming data to the programming input terminal to program the PLD in some desired way and then uses tester channels accessing the normal input and output terminals of the PLD to test its logic. To fully test a PLD, the tester programs the PLD for several different logic operations and tests the PLD's logic operation each time it is programmed.
The process of supplying programming data to a PLD programming input is similar to providing scan data to an IC scan terminal. Regardless of whether a tester supplies a serial data stream to a PLD programming terminal or to an IC scan input terminal, every channels vector memory must provide a vector for every programming or scan cycle and for every normal test cycle.
One method for reducing the need for large vector memories has been to provide a separate sequencer in each channel which can stop the flow of vectors at various times during a test. Assume for example that the first N cycles of a test are normal test cycles and the next M cycles of a test are scan test cycles. During the first test cycle, the sequencer in each channel read addresses the first address of the channel's vector memory so that it reads out a vector to the local pin electronics circuit. In the channels accessing scan terminals, that vector tells the pin electronics circuit to put the scan terminal in the state that is appropriate for normal test operations. During the next N-1 test cycles, the sequencer in each channel accessing a scan terminal simply holds its vector memory at the same address so that the vector at the first vector memory address is repeatedly sent to the pin electronics circuit. In the meantime during the first N test cycles the sequencer in each channel accessing a normal IC input or output terminal continues to increment the address of its local vector memory in the normal fashion so that it provides a sequence of vectors to the pin electronics circuit. On test cycle N+1, the sequencers in the channels accessing scan terminals begin incrementing their vector memory addresses so that the pin electronics circuit begins carrying out the scan test. The sequencers in the channels accessing normal IC input/output terminals stop incrementing their vector memories so that their pin electronics circuits continue to receive the vector at memory address N+1 during the M cycles of the scan test. Such a tester architecture is also useful in the context of testing PLDs since sequencers can halt the flow of vectors in channels accessing normal IC input/output terminals during programming cycles and can halt the flow of vectors in channels accessing PLD programming terminals during logic test cycles.
As PLDs increase in size the amount of programming data that must be supplied to a PLD can be very large, requiring more storage capacity than the vectors needed to test the PLD once it has been programmed. Some integrated circuit testers provide vector memories in the channels that are only large enough to hold the vectors needed for normal test cycles and provide a large central memory for storing scan or programming data. During the scan or programming phases of a test, a bus delivers the scan or programming data read out of the large central memory to the tester channel(s) accessing the scan or programming terminals of the device under test. During normal test cycles all channels obtain vectors from their local vector memories in the normal fashion.
Rather than directly storing the vector sequences needed to tell the channels to produce scan or programming data, the central memory directly stores the sequence of scan or programming data bits that the channels are to provide to the scan or programming terminals of the IC under test. As the scan or programming data arrives at a tester channel, a decoder converts each bit of the data to a vector appropriate to cause the local pin electronics circuit to send the scan or programming data bit to the IC. Since a multiple bit vector may be needed to tell a pin electronics circuit to generate single scan or programming data bit, it is more efficient to store scan or programming data than vectors in the central memory.
As IC and PLD's and the manner in which they are tested have become more complex, impractically large central memories are needed supply the channels with scan and programming data. What is needed is a system for economically storing and supplying very large amounts of scan or programming data to integrated circuit tester channels.